SUPER
Spectral Ultra-Packed Encoding Register
QUASAR · d=128 · GF(2⁷) · Region II challenging
SUPER is QLT's high-density 7-bit field-compute chip — GF(128) = GF(2⁷) on a 128-bin frequency-qudit at Δf = 35 GHz and Bcomb = 4.45 THz. The first chip where OPC + squeezing are mandatory (not optional boundary assists), ~16,384 pairwise phase relationships make STAR-PHASER linear calibration infeasible, and the STAR-PHASER crisis becomes visible on the roadmap between SUPER and THETA (d=256, Region III).
From SUPER upward, OPC + squeezing are MANDATORY — not optional. Distributed OPC mesh (32+ nodes, M=4 gate period) and ≥6 dB per-octet phase squeezing are co-equal with linear QFP gates. Without both layers, bounded-error recurrence fails across 16,384 phase relationships.
SUPER specification ledger
Canonical numbers from WS13 Δf table and S51–S60 corpus.
Q = (H_NL + H_OPC + H_CV) / H_linear Region I (STAR-PHASER): Q < 0.2 Region II (QUASAR): 0.2 – 1 ← SUPER lives here Region III (field): Q ≈ 1 ← THETA SUPER: mid Region II (Q ≈ 0.5). Nonlinear + CV share co-equal with linear. OPC+squeeze mandatory — not adjunct.
Lineage: NOVA (d=64, Region II entry) → SUPER (d=128, challenging) → STAR-PHASER crisis zone → THETA (d=256, field computing).
| Property | Value | Status |
|---|---|---|
| Hilbert dimension d | 128 = 2⁷ | designed/target |
| Algebraic layer | GF(128) = GF(2⁷), char 2 | roadmap |
| Bits / photon | 7 | info-theoretic |
| Comb spacing Δf | 35 GHz | designed/target |
| Comb span Bcomb | 4.45 THz (127×Δf) | model |
| OPC bandwidth margin | ~2.7× @ 12 THz (tight) | claim |
| Phase relationships | N(N−1) = 16,384 | model |
| FWM pathways | ~2.08M (d²(d−1)) | model |
| QFP cells (~Reck) | ~8,128 | model |
| OPC + squeezing | MANDATORY — 32+ OPC, 8 squeeze cells | designed/target |
| Primary fab gate | 128-ch routing (4×32 AWG tree) | flagged |
| Paradigm status | Crisis visible — linear extrapolation fails | strategic |
U-01 · U-02High-density compute thesis
S51 — why SUPER exists between NOVA and THETA.
Three hypotheses, one die
7-bit field · mandatory OPC+CV · paradigm break7-bit field arithmetic at photonic speed
→GF(128) GFADD/GFMUL, RS(127,·) syndrome extraction, and X₁₂₈/Z₁₂₈ stabilizers remain tractable when OPC pre-corrects phase across 16,384 pairwise relationships. Primitive polynomial p(x) = x⁷ + x + 1 committed globally; bin k labeled α^k.
How we do it: 7-bit symbol registers for GFADD/GFMUL kernels alongside SU(128) QFP cascade (S53).
Mandatory OPC + squeezing closes the 16k-phase gap
→Sparse witness inference (ChiL++ from NOVA ChiL) extends to O(N log² N) ≈ 1,800 measurements but requires sub-SQL homodyne and distributed squeeze mesh for witness SNR. OPC alone is insufficient at d=128.
Campaign rule: OPC + squeezing MANDATORY from SUPER up
OPC margin ~2.7× is survivable — barely
→4.45 THz comb still fits inside 12 THz FWM acceptance with engineered pump scheduling, but bin-nonuniform η on outer bins becomes the acceptance gate. SUPER asks: can Region II hold at 7-bit density before THETA forces continuous OPC?
128 bins, crosstalk risk & dense packing
S52 — densest frequency-bin lattice before THETA.
Single-photon qudit state: |ψ⟩ = Σk=0126 ck|fk⟩ with Σ|ck|² = 1. Bins separated by Δf = 35 GHz; comb spans Bcomb ≈ 4.45 THz — consuming ~37% of nominal 12 THz OPC acceptance.
p(x) = x⁷ + x + 1 (primitive over GF(2)) GF(128) ≅ GF(2)[x]/(p(x)) |f_k⟩ ↔ α^k for k = 0…126 (bin 127 = guard) N_FWM ≈ d²(d−1) = 128² × 127 ≈ 2,081,792 ≈ 2.08M
Critical honesty: Bin index k is not integer addition in GF(128). Gates implementing X₁₂₈ are SU(128) permutations, not field addition.
- Adjacent-bin crosstalk — 35 GHz spacing pushes AWG skirts into overlap; leakage Lij for |i−j|≤2 is primary error channel.
- FWM pathway explosion — ~2M degenerate four-wave-mixing channels create structured phase errors during OPC refresh.
- Phase cardinality — 16,384 pairwise relationships mean bin-local defects propagate globally.
| Δf | 35 GHz (tightened from NOVA) |
| Per-bin δf (filter) | ~15–20 GHz FWHM |
| Adjacent XT @ 35 GHz | target < 10⁻³ |
| OPC margin | ~2.7× (vs NOVA ~4×) |
How we do it: Phase-locked 128-line comb; mask-programmed k → 7-bit polynomial ROM; 4×32 AWG tree with ring-assist pre-filters; pump-null schedule for top-2,000 FWM pathways per cycle; mandatory squeeze per octet recovers 35 GHz XT budget.
U-03 · U-04SU(128) cascade & 7-bit symbol kernels
S53 — QFP universal control and GF(128) classical arithmetic layer.
| A — Clifford | X₁₂₈, Z₁₂₈, F₁₂₈, CNOT₁₂₈ |
| B — Field | GFADD, GFMUL, GFINV, GFFFT |
| C — Universal | SU(128) via Reck — tomography only |
# tunable cells ≈ d(d−1)/2 = 8,128 # OPC refresh every M = 4 layers (mandatory) # max depth between refresh ≈ 4 gates # V_∞ ≈ 0.996 with OPC+squeeze+pulsed η=0.9
Production SUPER runs Tier A + B frozen microprograms (~200 opcodes). Full Reck decomposition (253 stages) reserved for calibration tomography — never at runtime.
32-bit ISA word: 8-bit opcode · 7-bit src · 7-bit dst · 7-bit imm7 symbol. FAU hosts 127×127 log/antilog ROM (~16 KB BRAM per lane).
How we do it: Freeze Tier A+B microprograms; insert OPC every M=4 layers; certify Clifford generators via RB at d=128 (F > 0.999 for X/Z).
U-05 · U-06Large-scale spectral synthesis
S54 — 128-tooth comb, octet tiling, ~12×14 mm² die.
SUPER's source tile generates a phase-locked 128-tooth microcomb at 35 GHz spanning 4.45 THz — 2× NOVA source complexity. Tooth amplitude uniformity ±0.3 dB and CEO stability < 1 mrad/hr gate the entire 16,384-phase calibration budget.
| Ring radius R | ~685 µm (35 GHz FSR) |
| Die size | ~12×14 mm² |
| Octet blocks | 8 × 16 bins |
| OPC spirals | 32+ As₂S₃/AlGaAs nodes |
| Squeeze cells | 8 (1 per octet, ≥6 dB) |
- T-SUPER-A — source + 2 octets (32 bins) + 1 OPC node
- T-SUPER-B — full 8 octets + 4 OPC nodes; ChiL++ at 16k pairs
- T-SUPER-C — full die with squeeze mesh; mandatory CV validation
Research vehicle — not production v1. No full-die commitment until T-SUPER-A passes comb lock.
How we do it: Scale B07 Si₃N₄/TFLN flow; SFWM ring over-generate 150 lines, trim to 128; GPS-disciplined 35 GHz lock; 32+ OPC spirals distributed across octet blocks; 8 squeeze cells with Ge homodyne witness per octet.
U-07 · U-08Extreme 128-channel complexity
S55 — 4×32 AWG tree; routing is the dominant fab gate.
At d=128, routing escalates from "limiting" (TETRIS) to extreme. A single 128-ch AWG is infeasible — spectral resolution forces a 4×32 hierarchical tree with ring pre-filters per octet. Total demux IL budget: ~10 dB.
128 bins → [Octet pre-filter ×8]
→ [AWG-32 ×4: A/B/C/D]
→ [Ring assist ×8]
→ [128 SNSPD / 4×32 WTE]
Total IL waterfall ≈ 23.5 dB → photon survival ~1.3%
128-ch routing is the primary fab-yield gate at SUPER — more limiting than OPC bandwidth. AWG crosstalk leakage maps directly to pairwise phase errors in the 16,384 calibration matrix; routing and calibration are coupled subsystems.
SUPER's AWG-tree architecture is the last hierarchical routing solution before THETA forces global phase calibration.
How we do it: Design 4×32 AWG tree (XT < −24 dB adjacent @ 35 GHz); characterize 128×128 leakage matrix at fab; deploy 4×32 WTE readout with octet-sequential fallback; couple leakage matrix to ChiL++ inference engine.
U-09 · U-10~16,384 phase relationships & ChiL++
S56 — sparse witness inference at calibration cardinality limit.
| L0 — Comb lock | 2 global |
| L1 — Octet lock | 128 measurements |
| L2 — OPC witness | 32 nodes |
| L3 — Sparse pairwise | ~1,800 witnesses |
| L4 — Squeeze witness | 128 (Clifford-critical) |
| L5 — Inference engine | 8,128 θᵢ solve |
Brute-force calibration of 8,128 cells at 1 ms/cell = 2.3 hours per chip — unacceptable. ChiL++ reduces measurements to ~1,800 (~1.8 s) plus continuous OPC-as-sensor streaming.
Critical dependency: ChiL++ witness SNR requires ≥6 dB squeezing — without mandatory CV layer, witness measurements fall below inference threshold.
How we do it: Boot L0→L1→AWG alignment→squeeze activate; compute 1,800-pair spanning set; solve 8,128 θᵢ via mesh Jacobian at 1 kHz fast / 1 Hz full; acceptance: all 16,384 pairs < 0.05 rad.
U-11 · U-12Distributed OPC mesh + squeezing — not optional
S57 — the defining architectural shift from STAR-PHASER to QUASAR.
From SUPER upward, OPC + squeezing are MANDATORY — not optional boundary assists. Without both layers, SUPER cannot close the calibration or fidelity budget across 16,384 phase relationships. The chip does not function without both layers — this is not a performance upgrade.
| OPC nodes | 32+ (4 per octet) |
| Insertion period M | 4 gates (vs TETRIS M=10) |
| η (pulsed) | 10–90% |
| Comb-derived pumps | 128-tooth rotation |
| OPC margin | ~2.7× @ 12 THz |
| Squeeze cells | 8 (1 per octet) |
| Squeeze level | ≥6 dB phase squeezing |
| Homodyne taps | Ge PD per octet |
| Witness loop | 1 kHz fast / 1 Hz full |
| Q contribution | H_OPC+H_CV ≈ 35–40% |
OPC only (M=4, σ=0.08, η=0.5): V_∞ ≈ 0.97 → FAIL 16k pairs OPC + squeeze (M=4, σ=0.04, η=0.5): V_∞ ≈ 0.99 → marginal OPC+squeeze+pulsed (M=4, σ=0.04, η=0.9): V_∞ ≈ 0.996 → PASS
OPC lowers p_Z from ~35% to ~1–3%; squeezing improves witness SNR for ChiL++. Neither replaces GF(128) QEC (blocker #5).
How we do it: Place 32+ OPC nodes every 4 QFP layers; deploy 8 squeeze cells with Ge homodyne; rotate 128-tooth comb pumps with top-2,000 FWM nulls per cycle; pulsed OPC 10–90% η; sub-SQL witness loop feeds ChiL++; co-model with RS(127,119) decoder.
U-13 · U-14GF(128) coding theory & 7-bit syndrome richness
S58 — RS(127,119), stabilizers, erasure decoding at ~1.3% survival.
SUPER is the first chip where 7-bit syndrome richness makes QEC a genuine advantage — RS(127,119) with 4-symbol correction (28 bits), X₁₂₈/Z₁₂₈ qudit stabilizers, and ~240 ns total decode latency.
Layer 0: OPC conjugation → p_Z 35% → 1–3% Layer 1: Squeeze witness → calibration SNR Layer 2: RS(127,119) encode → 4-symbol correct Layer 3: X₁₂₈/Z₁₂₈ stabilizer → logical qudit Layer 4: Erasure detect → loss recovery Target: p_logical < 10⁻⁶ per gate
| GALAXY d=16 | 4-bit syndrome |
| TETRIS d=32 | 5-bit syndrome |
| NOVA d=64 | 6-bit syndrome |
| SUPER d=128 | 7-bit · 4-symbol RS |
| THETA d=256 | 8-bit · RS(255,223) |
OPC does not fix loss. At ~23 dB total IL, erasure decoding via GF(128) RS is mandatory.
How we do it: Encode every register in RS(127,119); run OPC+squeeze every 4 gates; extract syndrome via F₁₂₈ + GFFFT₁₂₈ (~35 ns); Berlekamp-Massey on FPGA (~100 ns); detect erasures via no-click events.
U-15 · U-167-bit symbol density & high-connectivity lattice
S59 — near-byte field compute; all applications roadmap until OPC+squeeze demonstrated.
- Cryptographic integrity — GF(128) universal hashing, 7-bit auth tags
- Synthetic lattice — 128-node graph state per photon; 128^N scaling
- Spectral AI primitives — MATMUL₁₂₈, FFT₁₂₈, DOT₁₂₈ (roadmap)
- Quantum chemistry — 7-orbital basis emulation (speculative)
- Telecom FEC precursor — RS(127,119) trials before THETA byte alignment
SUPER carries log₂(128) = 7 bits per photon — the densest QLT symbol before THETA's full byte alignment. Two entangled SUPER qudits span 16,384 complex amplitudes.
Honest posture: All SUPER applications are roadmap. First proof point: 7-bit universal hash on T-SUPER-B. Never state: "SUPER replaces GPU" or "photonic AES."
U-17 · U-18What goes inside SUPER
d = 128 · GF(27) · Region II · In Development · Die ~12×14 mm² · Δf = 35 GHz · Bcomb = 4.45 THz · 128-bin
SUPER scales NOVA’s recipe to 128 bins with mandatory squeezing
Phase A — FEOL: LIGENTEC AN800. 128-tooth microcomb ring (R≈685 µm), 4×32 AWG tree, 8 octet shaper banks, ~8,128 QFP MZI cells (Reck), ring-assist pre-filters.
Phase B — Active bond: QLT. 32+ distributed As₂S₃/AlGaAs OPC spiral nodes (M = 4). 8 squeeze cells (≥6 dB) bonded per-octet. Ge homodyne balanced taps.
Phase C — BEOL: TFLN EO modulators. Metal heater layer for >8,000 DAC channels. Hermetic seal prep.
Phase D — Assembly: 128-ch SNSPD / 4×32 WTE cryo module, fiber array, hermetic package.
Region II: squeeze + homodyne become mandatory
Squeezing: First chip where ≥6 dB squeeze per-octet is mandatory (not optional). 8 dedicated squeeze cells.
Comb: 128-tooth @ 35 GHz (narrower spacing vs NOVA’s 50 GHz). 4.45 THz total span.
OPC: 32+ distributed OPC spirals at M = 4 gate period — more aggressive than NOVA. OPC margin ~2.7×.
Homodyne: Ge balanced taps per octet for continuous-variable readout alongside SNSPD discrete detection.
LUV → QIL → FPGA + ASIC → SUPER photonic chip
.luv source → luvc build → QIL IR 0.1.0 · run_freqbin_shot (128-dim gate + squeeze path)
dac.voltages[8000+] → 128 per-tooth trims + OCT globals + OPC bias + squeeze biasqfp_schedule[] → GF(27) frequency-bin unitary programsshot_contract → 128-ch SNSPD pattern + homodyne quadrature + comb_lock gate
32+ As₂S₃/AlGaAs OPC spirals (M=4) · 8 squeeze cells (≥6 dB) · Ge homodyne taps
Where SUPER sits
7-bit density at the paradigm break
GEMINI is the shipping reference SKU. SUPER is the Region II stress vehicle where OPC + squeezing become mandatory and the STAR-PHASER linear recipe approaches its limit — diligence and research partners only.