STAR-PHASER GEMINI
QLT's only shipping STAR-PHASER product today: a room-temperature, dual-rail (d=2) photonic qubit processor in Region I (Q βͺ 0.2), where linear MZI circuits dominate and OPC acts as a passive phase pre-layer beneath digital QEC β not a replacement for it. One photon, two SiβNβ waveguides, SU(2) gates on an 8-mode Clements mesh, Type-II fusion entanglement, and warm InGaAs/GeSi SPAD readout at 15β45 Β°C.
G-01GEMINI v1 product parameters
Every value carries a status label. External benchmarks are cited for context β not claimed as QLT measurements unless noted.
| Parameter | GEMINI value | Status |
|---|---|---|
| Brand / codename | STAR-PHASER GEMINI | designed/target |
| Encoding | d=2 dual-rail path Β· |0β© rail A Β· |1β© rail B Β· 1 bit/photon | designed/target |
| Region / Q-metric | Region I Β· Q βͺ 0.2 (model β 0.05) | designed/target / model |
| Die footprint | 5 Γ 5 mm | designed/target |
| Operating temperature | 15β45 Β°C warm core (mesh, sources, SPAD) | designed/target |
| Wavelength | C-band ~1550 nm | designed/target |
| Gate mesh | 8-mode Clements/Reck Β· 28 MZIs Β· 32 thermo-optic heaters | designed/target |
| Switches | 16 (feed-forward + K=8 mux tree) | designed/target |
| Detectors | 16 on-chip SPAD taps; Ge homodyne optional (CV path) | designed/target |
| Sources | K=8 heralded SFWM rings + T=4 temporal slots | designed/target |
| Multiplexed availability | A β 96.6% at p=0.1, K=8, T=4 | model |
| OPC geometry | Recirculating storage loop Β· M β 10 gates | claim/to-be-tested |
| Gate depth (phase / with OPC) | ~50β100 / 500β1,000+ gates | external limit / designed/target |
| v1 quantum demo | 4-qubit GHZ >85% fidelity | designed/target |
| Dual-use AI mode | Same mesh β photonic AI accelerator (~14 TOPS/W class) | designed/target |
| Ξf (frequency-bin) | N/A β path encoding, no comb | designed/target |
| External benchmark (SPAM) | β | PsiQuantum Omega: 99.98% external |
| External benchmark (fusion) | β | PsiQuantum Omega: 99.22% external |
Full platform walkthrough: How We Do ItChips & Mfg OverviewChip Lineup Β· Roadmap ladder: Base 2 β GF(256) Β· Chip lineup: STAR-PHASER chips
Eight subsystems on one die
Tap any tile to expand. Each section maps to a WS13 research memo β encoding through applications.
GEMINI stays in Region I: purely linear interferometry between sparse OPC nodes. No frequency-bin routing, no QFP shaper cascades β those belong to SOLAR+ roadmap chips.
GEMINI subsystem stack
Encoding Β· gates Β· source Β· routing Β· cal Β· OPC Β· QEC Β· appsDual-rail path encoding physics
βOne qubit = one photon in a two-dimensional path Hilbert space: |Οβ© = Ξ±|1β©A|0β©B + Ξ²|0β©A|1β©B. Quantum information lives in the amplitude ratio |Ξ±/Ξ²| (population) and differential phase ΞΟ = ΟA β ΟB (Bloch equator). Global phase ΟA + ΟB is unphysical β it cancels in all interferometric readouts.
Loss on one rail without heralding is an erasure β the photon left the {|0β©,|1β©} subspace but the defect location is known, which QEC treats more favorably than undetected depolarizing noise. Heralding + coincidence filtering enforce the single-photon subspace at runtime.
d=2 Β· SU(2) Β· no spectral crosstalk Β· no EOM scattering
Upgrade path: optional GAP4 transcode at encoding boundary β 2-color frequency qubit β open comb (d=10, SOLAR roadmap). Native GEMINI computation skips the transcoder entirely.
MZI mesh, SU(2) gates, Type-II fusion
βSingle-qubit gates are programs on an 8-mode Clements mesh (28 MZIs, 32 thermo-optic heaters). Arbitrary U(2) per dual-rail pair decomposes into directional couplers (beam splitters) and one-rail phase shifters β Hadamard, Rz, Clifford+T all compile to mesh DAC tables.
Two-qubit entanglement is measurement-based, not deterministic Οβ½Β³βΎ CZ: Type-II fusion Bell measurements (Psucc = Β½ ideal passive LO) + TFLN feed-forward (~11.2 ns budget) steer partner photons in delay spirals. External ceiling: 99.22% fusion fidelity on manufacturable Si (Giewont et al., 2024) β GEMINI targets >99% post-characterization.
Depth without OPC: V(N) = exp(βNΟΒ²/2) Β· with OPC every Mβ10: Vβ = exp(βMΟΒ²/2Ξ·)
v1 demo: 4-qubit GHZ >85% fidelity on modes 1β8 (four dual-rail pairs).
Heralded SFWM Β· K=8/T=4 multiplexing
βEight independent SiβNβ micro-rings (R β 50 Β΅m, Q > 5Γ10β΅) produce heralded pairs via Οβ½Β³βΎ SFWM at mW-class C-band pumps. Idler clicks flag signal photons; FPGA schedules delivery through a three-stage binary switch tree (7 TFLN EO routers) with T=4 temporal retry slots per source.
Availability law: A = 1 β (1 β p)KΒ·T. At p=0.1, K=8, T=4 β A β 96.6% [model]. Absolute photon-at-output probability PG1 remains switch-loss-limited (~47% [model]) β publish both A and PG1 separately on datasheets.
GEMINI deliberately uses spatialΓtemporal mux β not Fan 2025 spectral state-multiplexing (roadmap SOLAR path). Ξf = N/A on this SKU.
Fab: LIGENTEC AN350-class MPW + proprietary TFLN bond + optional AsβSβ OPC overlay (~34-week defer-AsβSβ track available).
Classical switching & interferometric transport
βTwo routing regimes on one chip: (1) classical path selection β herald-driven mux tree and feed-forward switches route which mode carries the photon without entangling; success requires low IL, high extinction, phase-stable equalized paths. (2) coherent superposition β MZI mesh routes amplitudes between rails; errors are multiplicative in gate fidelity.
K=8 / 3-stage tree = minimum depth for eight independent herald arms. Per-stage IL target <0.5 dB; extinction >20 dB; path skew Β±0.5 Β΅m. Source-stage OPC erases route-dependent phase so muxed photons remain mutually indistinguishable for HOM/fusion.
No 10-ch / 64-ch WDM demux on GEMINI β purely spatial until SOLAR
Technology-agnostic switch socket (P3): TFLN EO committed for mux + feed-forward; thermo-optic for gate mesh; MEMS for lab bring-up only.
Control stack Β· GAP5 self-calibration probe
βControl loop: SPAD clicks β 64 ps TDC β FPGA (herald decode, mux select, FF LUT) β AD5372 DAC (32 mesh heaters). Full thermal mesh refresh ~54 Β΅s; feed-forward decision ~11.2 ns (FPGA-limited, switch <2% of budget).
GAP5 OPC visibility probe: V = exp(βΟΟΒ²/2) reports differential phase variance from heralded HOM interference β zero added test structures, in-situ during production operation. Drift alarm triggers DAC recalibration when V drops below threshold.
Calibration layers: fabrication trim (once per die) β periodic thermal sweep β mux path equalization (bright-pulse boot) β GAP5 in-situ witness β source_id coincidence validation every shot.
T9 gate: single-photon HOM before/after OPC on dual-rail Sagnac node
OPC lattice Β· periodic conjugation Β· baseline CV
βHybrid SiβNβ/AsβSβ FWM nodes at mux output (GAP2 source-stage) and every M β 10 gates in a recirculating storage loop (GAP1 lattice). Phase conjugation: Ο β βΟ on each rail; differential encoding lets common-mode pump phase cancel in symmetric layouts.
Without OPC: Var(Ο) = NΒ·ΟΒ² β visibility collapses ~50β100 gates. With OPC every M gates: Vβ β€ exp(βMΟΒ²/2Ξ·) β error bounded by interval M and efficiency Ξ·, not total depth N.
Optional CV path: Ge p-i-n balanced homodyne @ 15.3 GHz for quadrature readout β baseline CV hardware, not fault-tolerant GKP on shipped SKU. OPC preserves quadrature structure (Gaeta & Boyd, 1995 theory).
Single-photon OPC on-chip: [to-be-tested] Β· Campaign T9 gates all high-d OPC claims
Never state: OPC replaces QEC β it is an analog phase pre-layer beneath digital stabilizer extraction.
Surface code / stabilizer baseline
βPhysical qubit: dual-rail d=2. Stabilizer codes: surface, LDPC, XZZX (bias-aware β OPC Z-preference). Syndrome extraction reuses ancilla MZI programs + per-rail SPAD clicks β FPGA Pauli frame (Path A, v1 ship path).
Industry FT destination (Path B, roadmap): fusion-based quantum computation (FBQC) where resource-state tiles + Type-II fusions encode foliated surface codes β syndromes read from fusion outcomes. GEMINI v1 ships primitives only, not a fault-tolerant fusion network.
Loss maps to heralded erasure (cheap, ~25β50% theory threshold class). Post-OPC model: pZ ~35.7% β ~1.2% at Ξ·β₯0.5 β moves operating point toward surface-code Pauli threshold (~1%). A507 Stim/PyMatching simulation is software gating.
Logical qubit / break-even QEC: [roadmap] β not GEMINI ship date
Applications Β· validation Β· dual-use AI
βTier A β ship today: dual-rail LOQC processor; photonic AI inference on same 28-MZI mesh (configuration change: pump power, detector mode). Tier B β validation: 4-qubit GHZ >85%, HOM >85%, gΒ²(0)<0.5, CAR >50:1. Tier C β roadmap: decimal/GF compute β SOLAR / NOVA.
Validation hierarchy gates marketing: Layer 1 timing β Layer 2 mesh cal β Layer 3 OPC probe (T9) β Layer 4 fusion+FF β Layer 5 GHZ/algorithms β Layer 6 FBQC factory [roadmap]. Do not skip to Layer 5 claims without Layer 3 evidence when OPC is featured.
External GHZ benchmark: 85.4% integrated Si (2024) β GEMINI >85% target is competitive with integrated photonics SoTA, not bulk telecom or cryo SNSPD platforms.
Customer personas: HPC pilot (no cryoplant), photonic QC research lab, AI/accelerator dual-use, government eval on US-friendly split-fab.
G-09
G-15
G-08What goes into GEMINI β and when
Every component that enters the build, organized by manufacturing phase. From foundry wafer to shipping product.
Manufacturing build sequence
FEOL Β· bond Β· BEOL Β· assembly Β· electronics Β· softwareSilicon nitride photonic backbone
βFoundry: LIGENTEC AN800 MPW β X-FAB Erfurt 200 mm wafer line. Shuttle LGT-MPW-AN800-44 (registration closes 1 Jul 2026). Backup: AIM Photonics.
SiβNβ strip waveguides β 800Γ400 nm, stoichiometric LPCVD, <0.5 dB/m propagation loss. Forms the entire passive backbone.
8 SFWM microrings β Rβ50 Β΅m, Q>5Γ10β΅, Οβ½Β³βΎ photon-pair sources. Each ring generates heralded single photons at C-band ~1550 nm.
28-MZI Clements mesh β 8-mode interferometric unitary. Directional couplers + thermo-optic phase shifters implement arbitrary SU(8) gates.
32 TiN thermo-optic heaters β ~54 Β΅s settle time. Driven by AD5372 DAC via SPI. Each heater controls one MZI arm phase.
Feed-forward delay spirals β on-chip optical delay lines matched to the ~11.2 ns SPADβFPGAβEOM feed-forward loop.
Encrypted GDS-II sent to foundry β OPC geometry withheld. Foundry never sees arsenic or nonlinear overlay.
TFLN electro-optic switch layer
βTFLN thin film β 300β600 nm thin-film lithium niobate, ion-cut bond onto SiN at β€500 Β°C. Coupon placement via X-Celeprint micro-transfer printing (MTP).
23 TFLN EO switches β sub-nanosecond switching, >110 GHz bandwidth. 7 multiplexer switches route heralded photons; 16 feed-forward switches implement conditional corrections.
Ti/Au GSG electrodes β 200/500 nm, e-beam evaporation + lift-off. 16 RF ground-signal-ground pads drive the EO switches.
Bond performed in QLT cleanroom β β€500 Β°C max, well below AsβSβ Tg.
AsβSβ chalcogenide OPC overlay
βAsβSβ overlay β 6N-purity arsenic trisulfide, 450β550 nm thickness. Thermal evaporation at <210 Β°C (golden rule: no processing above Tg after deposition). n=2.40, nβ=2β5Γ10β»ΒΉβΈ mΒ²/W.
4 FWM-OPC sites β four-wave mixing optical phase conjugation nodes placed every ~10 gates. Recirculating OPC loop geometry enables Mβ10 conjugation passes.
MES barcode lockout enforces golden rule β furnace interlock prevents wafer entry above 210 Β°C.
Packaging, fiber attach, detector bond
βDie: 5Γ5 mm single tile, diced on DISCO DAD-3220.
Hermetic butterfly package β CVD diamond heat spreader, <0.5 W total dissipation. Kovar-sealed.
Fiber array β SMF-28 (Corning), ExSpot inverse-taper edge coupling. Aligned on PI P-611 NanoCube 6-DOF stage.
SPAD flip-chip bumps β 24 In/Sn bumps (8 herald + 16 mesh), PDE β₯28%. Bonded on SΓSS FC150 at Β±1 Β΅m accuracy.
Au wire bonds β 32 heater pads + 16 RF GSG pads, 25β50 Β΅m Au wire via K&S 4523 bonder.
Hermetic seam-seal β final enclosure, leak-tested.
Control hardware, lasers, detectors
β2Γ Analog Devices AD5372 Rev. C β 32-channel 16-bit DAC, SPI @ 50 MHz, 0β5 V output, LDAC-synchronized. 64 total channels drive 32 TiN heaters with ~54 Β΅s full mesh refresh.
FPGA (prototype): AMD/Xilinx Artix-7 XC7A100T on Digilent Arty A7-100T dev board β 101k logic cells. Herald engine, DAC SPI master, TDC decode.
FPGA (production): AMD/Xilinx Kintex-7 XC7K325T on AMD KC705 β 326k cells, FMC DAC daughter-card, GTX transceivers. Toolchain: AMD Vivado, Verilog/SystemVerilog, XDC timing constraints.
Supervisor MCU: STMicro STM32H7 Cortex-M7 β housekeeping, DFU firmware update, calibration storage, USB-C / UART / IΒ²C interfaces.
Custom 16-ch TDC ASIC β 64 ps time bins, 33-bit words (channel + 16-bit coarse + 9-bit fine), LVDS output to FPGA.
CW pump laser: Santec TSL-570 β 1550 nm, 150 mW, PM fiber output. Drives SFWM photon-pair generation.
Mode-locked clock: Menlo Systems C-fiber β 100 MHz rep rate, 150 fs pulses, 16 control fibres. Provides optical clock for feed-forward timing.
SPAD module: Aurea Technology 12-ch gated InGaAs (primary) β 1550 nm, PDE β₯30%, DCR <2 kHz, gate 1β10 ns. Parallel eval: ID Quantique 12-ch. Backup: MPD PDM-IR.
Compiler β middleware β firmware integration
βLUV Language v0.3 β user writes .luv source β luvc build β QIL IR 0.1.0 bundle. Commands: luvc check, luvc build, luvc run, luvc fmt.
QIL Middleware β three artifact contract: dac.voltages[32] (28 Clements phases β crosstalk-corrected 0β5 V for AD5372), qfp_schedule[] (ordered unitary steps), shot_contract (SPAD herald pattern).
FPGA firmware β herald engine, DAC SPI master (2Γ AD5372), TDC decode, BRAM LUT, feed-forward loop. 200 MHz clock domain. AMD Vivado toolchain.
Three timing tiers:
Feedforward ~11.2 ns β when after measure β Aurea SPAD β TDC β FPGA BRAM β Menlo trigger β TFLN EO switch
Reconfiguration ~54 Β΅s β mesh, phases β FPGA SPI β 2Γ AD5372 DAC β 32 TiN heaters
Environment <30 s β 16 min β comb_lock.grid_valid β TEC loop β band heaters β per-tooth servo
From GEMINI to the full platform
GEMINI is the shipping anchor. Explore the photon journey, roadmap ladder, sibling chips, and manufacturing path.
How We Do It
Complete walkthrough of heralded SFWM, OPC lattice, MZI mesh, detection, and feed-forward β the shared backbone GEMINI configures for minimum nonlinear budget (Region I).
Base 2 β GF(256)
GEMINI is Rung 0 (dual-rail, ships). SOLAR opens the comb to d=10; GALAXYβNOVA climb to GF(64) field coding β all proposal-grade beyond GEMINI.
STAR-PHASER & QUASAR lineup
Eight gate-locked chip pages from GEMINI (d=2, ships) through LOTUS (d=512, Region IV). Only GEMINI is solid today; all others ghosted roadmap.